1. Field of the Invention
The present invention relates to a structure of a semiconductor integrated circuit comprising at least two thin film transistors (abbreviated hereinafter as “TFTs”) on a same substrate, and to a process for fabricating the same. The semiconductor integrated circuit according to the present invention is utilized, for example, in active matrices of liquid crystal displays.
2. Prior Art
Prior art TFTs have been fabricated heretofore by patterning a thin film semiconductor region (active layer) into an island-like shape to isolate the region from other TFTs, depositing an insulating film as a gate dielectric on the region by CVD or sputtering, and then forming thereon a gate electrode.
FIG. 2 shows the process for fabricating a semiconductor integrated circuit comprising a TFT according to a prior art process. Referring to FIG. 2, a base film 22 and a silicon film 23 are formed on a substrate 21. Then, films 24a and 24b made of a material such as a photoresist are formed selectively on the silicon film 23. A thin film of silicon oxide or silicon nitride can be formed between the silicon film 23 and the films 24a and 24b to prevent the silicon film from being polluted (FIG. 2(A)).
The silicon film 23 is etched thereafter to form island-like silicon regions (active layers) 25a and 25b using the films 24a and 24b as the masks, however, the base layer 22 is etched partially at the same time. Thus, the step height increases by the over-etched portion x in addition to the thickness of the silicon film (FIG. 2(B)).
Then, an insulating film 26 which functions as a gate dielectric is formed over the entire surface to form a gate electrode with lines 27n, 27p, and 27c. Line disconnection may occur in case the active layer is provided with too large a step height.
After forming the gate electrode, impurities are introduced by means of, for example, ion doping or ion implantation. The resulting structure thus obtained is subjected to activation treatment by, for example, thermal annealing, laser annealing, or lamp annealing to form impurity regions 28n (n-type) and 28p (p-type).
Subsequently, an interlayer insulator 29 is deposited to form contact holes therethrough, and electrodes 30a, 30b, and 30c are formed in the impurity regions of the TFT.
In the prior art processes, however, the overetching of the base film has been found a problem. The presence of a step due to the overetching causes disconnection on the gate electrode to considerably impair the product yield. A step with a further increased step height produces in particular when a film having a high etching rate is used as the base film. Accordingly, though the use of a film deposited by plasma CVD or APCVD is preferred as the base film from the mass productivity point of view, these types of films are not preferred from the aforementioned problem of high etching rate. Thus, an object of the present invention is to review the problems in the prior art process for element isolation, and to provide a TFT of high product yield and a process for fabricating the same.